To ensure error-free data transmission, very stringent requirements are placed on the accuracy and stability of such clock generators. It is known, for example, to use microprocessor-controlled digital phase-locked loops for these purposes, see Ernst, W., Hartmann, H. L., "Neue Taktgeneratoren fur EWSD", telcom report 9 (1986) Heft 4, pp. 263-269. In such clock generators, contradictory requirements are placed on the phase-locked loop. On the one hand, the bandwidth of the phase-locked loop should be as wide as possible to meet the requirements regarding the time interval error (TIE), and on the other hand, the bandwidth should be as narrow as possible to minimize the effect of jitter and wander on clock accuracy in the event of a failure of the external reference clock signal. To be able to meet these contradictory requirements, very expensive high-stability crystal oscillators are used in conventional clock generators, but with the trade-off that, particularly in the event of a failure of the reference clock, deviations of the clock frequency become effective which are due to the properties of the crystal oscillator, such as its inherent stability.